1. Field of the Invention
The present invention relates to a semiconductor device and a method of increasing a breakdown voltage of the semiconductor device and, more particularly, to a high-breakdown voltage semiconductor device having a perfect dielectric isolation structure using an oxide-film-bonded substrate, and a method of increasing a device breakdown voltage of the semiconductor device, and a method of decreasing an ON resistance of a lateral MOSFET.
2. Description of the Related Art
As the number of functions as well as the integration density of a semiconductor integrated circuit are increased, the application range of an element isolation technique has been extended.
FIG. 1 is a sectional view showing schematically an element isolation structure consisting of a P-N junction and a biasing method thereof. An N-type epitaxial layer is deposited on a P-type semiconductor substrate 1. A P.sup.+ -type isolation diffusion layer 3 is formed from the major surface of the N-type epitaxial layer to reach the P-type substrate 1 and to surround an element region 2 of the N-type epitaxial layer. In the element region 2, a P.sup.+ NN.sup.+ diode is formed. An NPN transistor is formed in practice since, a breakdown voltage of only a collector junction may be often considered. For this reason, a P.sup.+ -type region 4, the N-type region 2, and an N.sup.+ -type region 5 of the diode are called a P.sup.+ -type base region 4, an N-type collector region 2, and an N.sup.+ -type collector region 5, respectively, for descriptive convenience. Reference symbols b and c also denote a base electrode terminal and a collector electrode terminal, respectively. The IC having a P-N junction isolation structure shown in FIG. 1 is generally used such that the minimum potential of the power supply voltage of the IC is applied to the P-type substrate 1. For example, when a power supply voltage is .+-.15 V, a voltage of -15 V is applied to the substrate 1. When only a power supply having a voltage +5 V is used, a bias voltage of 0 V (GND) is applied to the substrate 1. In FIG. 1, the negative terminal of a bias power supply V.sub.cb and a terminal S of the substrate 1 are grounded, and the potential of the P-type substrate 1 is fixed to be 0 V (GND). For this reason, the P-type substrate 1 and the N-type collector region 2 are normally set in a reverse bias state, thereby isolating the substrate 1 from the collector region 2 by a depletion layer. Note that this biasing method is a patent of Texas Instruments.
Drawbacks of the above conventional P-N junction isolation structure are roughly classified into a parasitic element effect and an increase in breakdown voltage of an element. First, in the parasitic element effect, although the potentials of the P-type substrate 1 and the P.sup.+ -type isolation diffusion layer 3 are fixed to be the minimum potential of the element region, a thyristor operation or a latch-up operation of a CMOS transistor is easily caused since a PNP parasitic transistor and the like are formed in the element formed in the element forming region 2. In order to avoid this drawback, a circuit design is inevitably restricted. In order to increase the breakdown voltage of the element, as shown in FIG. 2, the structure in which is an N.sup.+ -type buried layer 1a is formed in a P-type substrate 1 and an N-type epitaxial layer 2 is grown on the buried layer 1a is often used in the P-N junction isolation structure. In this case, a device breakdown voltage depends on the impurity concentration N and thickness t.sub.VG of an N-type epitaxial layer, i.e., an N-type collector region 2. The above breakdown voltage is represented by a bias voltage V.sub.cb obtained when a junction between a P.sup.+ -type base region 4 and the N-type collector region 2 is broken down.
FIG. 3 is a graph used for design of the breakdown voltage when the diode shown in FIG. 2 is formed in the stacked substrate consisting of the N-type epitaxial layer 2, the N.sup.+ -type buried layer 1a, and the P-type substrate 1. In this graph, the abscissa represents an impurity concentration N.sub.sub of the N-type epitaxial layer 2, the ordinate represents a breakdown voltage BV (V), and a parameter t.sub.VG (.mu.m) is the thickness of the N-type epitaxial layer 2. Note that the breakdown voltage BV (V) is a voltage V.sub.cb obtained when a depletion layer 6 reaches the N.sup.+ -type buried layer 1a. This is called a reach through. For example, in a device having a breakdown voltage of 500 V, assuming that, as shown in FIG. 3, the concentration N.sub.sub =4.times.10.sup.14 atoms/cm.sup.3 (a resistivity .rho..sub.sub is almost 10 .OMEGA..cm) is satisfied, the thickness t.sub.VG of 33 .mu.m or less is required to prevent the depletion layer 6 from reaching through the n.sup.+ -type buried layer la when the reverse vias voltage V.sub.cb is applied.
In general, a high-breakdown-voltage IC must be designed so that the depletion layer 6 reaches through the n.sup.+ -type buried layer la when a bias voltage near the breakdown voltage is applied. For this restriction, when high-breakdown-voltage elements each having a breakdown voltage of 500 V or more are to be integrated into an IC, the thickness t.sub.VG of the N-type epitaxial layer 2 must be set to be 30 .mu.m or more. In this case, an effective element area is disadvantageously decreased due to lateral diffusion when P.sup.+ -type diffusion is performed to a depth of 30 .mu.m or more to form the P.sup.+ -type diffusion layer 3. Even when deep trench isolation free from lateral diffusion is performed, i.e., isolation is performed by a deep insulator buried layer, the depth of a trench must be set to be 30 .mu.m or more. The present trench technique cannot form this deep trench. In an IC having a P-N junction isolation structure, the thickness of an N-type epitaxial layer must be increased to obtain a high breakdown voltage. As a result, the depth of a P.sup.+ -type isolation diffusion layer is increased. The lateral diffusion of the diffusion layer is thus increased, thereby decreasing the effective element area. Consequently, an element having a high breakdown voltage cannot be obtained in practice.
On the other hand, there is a strong market need for a technical means for decreasing an area required for element isolation to increase an effective element area and to obtain a high breakdown voltage. As an element isolation structure to cope with this need, there is proposed a perfect dielectric isolation structure obtained by combining a deep trench and a composite semiconductor substrate obtained such that an oxide film is sandwiched and bonded between semiconductor substrates.
FIG. 4 is a sectional view showing a structure of a conventional semiconductor element having a perfect dielectric isolation structure. An element forming region which in surrounded by an insulator isolation trench 15 and an oxide interlayer 13 is formed in a N-type semiconductor substrate 12. A composite semiconductor substrate consists of the N-type first semiconductor substrate 12, the oxide interlayer 13, and an N- or P-type second semiconductor substrate 11. When an NPN transistor is to be formed in the element forming region, a P-type base region 16 and an N.sup.+ -type collector region 19 are formed in the first semiconductor substrate 12, and an N.sup.+ -type emitter region 38 is formed in a P-type base region 36. An N.sup.+ -type buried layer 14 and a deep N.sup.+ -type layer 17 are formed inside the oxide film 13 to form a current path for preventing saturation of a voltage V.sub.ce in an ON state. The collector region 19 is formed in contact with the layer 17. In this conventional element, since a depletion layer is stopped at the N.sup.+ -type buried layer 14, a full depletion does not occur. The breakdown voltage of the element is disadvantageously low. In order to increase the breakdown voltage, the thickness of the first semiconductor substrate 12 must be increased. This fails to increase an integration density.